For decades, capacitors have been an important and irreplaceable circuit element used often in semiconductor circuit designs. For example, capacitors are widely used in applications such as dynamic random access memory (DRAM), active and passive filters, analog-to-digital and digital-to-analog converters (A/D and D/A converters, respectively), operational amplifiers, radio and tuning circuits, oscillators and multivibrator circuits, time critical and time delay circuitry, noise reduction circuitry, charge pumps, power electronics, and many other diverse applications. A capacitor is defined in the simplest terms as a device consisting of two conducting surfaces separated by an insulating material. A capacitor stores electrical energy or charge, blocks the flow of direct current (DC), and permits the flow of alternating current (AC) depending essentially upon the capacitance of the device and the frequency of the incoming current or charge. Capacitance, measured in farads, is determined by three physical characteristics: (1) a thickness or average thickness of the insulating material separating the two conducting surfaces; (2) how much surface area is covered by the two conducting surfaces; and (3) various mechanical and electrical properties of the insulating material and the two conducting plates or electrodes.
In the early development and marketing of the above mentioned technologies, parallel plate or parallel electrode capacitors were used as a capacitance structure. The parallel electrode capacitor is a capacitor that has a planar top and a planar bottom conducting surface separated by a planar dielectric or insulator. Because the parallel electrode capacitor is completely planar, large surface areas of substrate material or substrate-overlying layers of material are consumed to achieve capacitance values in a useful nanofarad or picofarad range.
DRAM memory cell substrate area reduction is very critical in order to achieve device densities that allow for a DRAM circuit with a large amount of memory cells. To achieve DRAM memory circuits with a million bits of storage or more, the industry developed a trench capacitor. The trench capacitor is formed by first etching a deep well, trench, or hole in a substrate surface or a surface overlying the substrate surface. This trench or hole is then used to form and contain two electrodes separated by an insulator. Because sidewalls of the trench or hole provide surface area to the capacitor without consuming more substrate surface area, the trench capacitor reduced capacitor substrate surface area and reduced the size of standard DRAM memory cells. Although trenches resulted in reductions in surface area, other methods described below are usually more efficient in enabling the manufacture of DRAM memory cells with reduced substrate area.
In order to achieve further reduction in DRAM cell sizes the industry developed a fin capacitor. The fin capacitor is formed by creating a first electrode overlying the substrate surface which resembles a vertically oriented comb-like structure. A central vertical pillar or spine of conducting material electrically connects to several horizontally positioned fins or planes of conducting material to form the comb-like structure. A second electrode is formed overlying the substrate in a vertical comb-like structure similar to the first electrode. The one difference between the two comb-like structures is that the fins of the first structure separate the fins of the second structure, or in other words, the fins from the two structures are intertwined thereby maximizing the surface area that the fins contribute to device capacitance. The fin capacitor device tended to be very complex and also limiting due to its geometric shape and fabrication scheme.
The semiconductor industry, in order to further improve the area savings and reduce overlying layer complexity, developed a "double box" capacitor and a few other vertically raised capacitors. The double box capacitor is created by lithographically forming a first box of conductive material with four sides. The four sides of this first box, which rise vertically above the surface of the substrate, surround another solid vertical lithographically-defined second box of conductive material. The first and second boxes are electrically connected to form a bottom electrode. An insulator covers the first and second boxes, and an overlying conductive layer forms the second capacitor electrode. In addition, structures similar to the double box capacitor have been taught. For example, U.S. Pat. No. 5,047,817, issued in September, 1990, by Wataru Wakamiya et al, entitled, "Stacked Capacitor for Semiconductor Memory Device," teaches a vertically raised capacitance structure.
Although the capacitors mentioned above offer surface area savings, they are: (1) limited by lithography; (2) in most cases lithographically intensive; (3) not space efficient enough for future memory generations; (4) result in topographical problems due to large vertical differences in height across the capacitive devices; and (5) tend to be mechanically more unstable as topography increases and therefore less manufacturable.